说明

• Circuit uses a direct digital synthesizer (DDS) with sub-Hertz tuning resolution as a low jitter sampling clock source for high performance ADCs. The AD9515 clock distribution IC provides PECL logic levels to the ADC. The AD9515 internal divider feature also allows the DDS to run at a higher frequency into the AD9515 front end, effectively increasing input slew rate. A higher slew rate into the AD9515 input squaring circuit can help reduce broadband jitter in the clock path