首先附上厂家提供的完整的dm9000程序:
1 /*
2
3 dm9ks.c: Version 2.08 2007/02/12
4
5 A Davicom DM9000/DM9010 ISA NIC fast Ethernet driver for Linux.
6
7 This program is free software; you can redistribute it and/or
8 modify it under the terms of the GNU General Public License
9 as published by the Free Software Foundation; either version 2
10 of the License, or (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17
18 (C)Copyright 1997-2007 DAVICOM Semiconductor,Inc. All Rights Reserved.
19
20 V2.00 Spenser - 01/10/2005
21 - Modification for PXA270 MAINSTONE.
22 - Modified dmfe_tx_done().
23 - Add dmfe_timeout().
24 V2.01 10/07/2005 -Modified dmfe_timer()
25 -Dected network speed 10/100M
26 V2.02 10/12/2005 -Use link change to chage db->Speed
27 -dmfe_open() wait for Link OK
28 V2.03 11/22/2005 -Power-off and Power-on PHY in dmfe_init_dm9000()
29 -support IOL
30 V2.04 12/13/2005 -delay 1.6s between power-on and power-off in
31 dmfe_init_dm9000()
32 -set LED mode 1 in dmfe_init_dm9000()
33 -add data bus driving capability in dmfe_init_dm9000()
34 (optional)
35 10/3/2006 -Add DM8606 read/write function by MDC and MDIO
36 V2.06 01/03/2007 -CONT_RX_PKT_CNT=0xFFFF
37 -modify dmfe_tx_done function
38 -check RX FIFO pointer
39 -if using physical address, re-define I/O function
40 -add db->cont_rx_pkt_cnt=0 at the front of dmfe_packet_receive()
41 V2.08 02/12/2007 -module parameter macro
42 2.4 MODULE_PARM
43 2.6 module_param
44 -remove #include 45 -fix dmfe_interrupt for kernel 2.6.20 46 V2.09 05/24/2007 -support ethtool and mii-tool 47 05/30/2007 -fix the driver bug when ifconfig eth0 (-)promisc and (-)allmulti. 48 06/05/2007 -fix dm9000b issue(ex. 10M TX idle=65mA, 10M harmonic) 49 -add flow control function (option) 50 10/01/2007 -Add #include 51 -Modyfy dmfe_do_ioctl for kernel 2.6.7 52 11/23/2007 -Add TDBUG to check TX FIFO pointer shift 53 - Remove check_rx_ready() 54 - Add #define CHECKSUM to modify CHECKSUM function 55 12/20/2007 -Modify TX timeout routine(+)check TCR&0x01 56 57 */ 58 59 //#define CHECKSUM 60 //#define TDBUG /* check TX FIFO pointer */ 61 //#define RDBUG /* check RX FIFO pointer */ 62 //#define DM8606 63 64 #define DRV_NAME 'dm9KS' 65 #define DRV_VERSION '2.09' 66 #define DRV_RELDATE '2007-11-22' 67 68 #ifdef MODVERSIONS 69 #include 70 #endif 71 72 //#include 73 #include 74 #include 75 #include 76 #include 77 #include 78 #include 79 #include 80 #include 81 #include 82 #include 83 #include 84 #include 85 #include 86 #include 87 88 #ifdef CONFIG_ARCH_MAINSTONE 89 #include 90 #include 91 #include 92 #endif 93 94 95 96 /* Board/System/Debug information/definition ---------------- */ 97 98 #define DM9KS_ID 0x90000A46 99 #define DM9010_ID 0x90100A46 100 /*-------register name-----------------------*/ 101 #define DM9KS_NCR 0x00 /* Network control Reg.*/ 102 #define DM9KS_NSR 0x01 /* Network Status Reg.*/ 103 #define DM9KS_TCR 0x02 /* TX control Reg.*/ 104 #define DM9KS_RXCR 0x05 /* RX control Reg.*/ 105 #define DM9KS_BPTR 0x08 106 #define DM9KS_FCTR 0x09 107 #define DM9KS_FCR 0x0a 108 #define DM9KS_EPCR 0x0b 109 #define DM9KS_EPAR 0x0c 110 #define DM9KS_EPDRL 0x0d 111 #define DM9KS_EPDRH 0x0e 112 #define DM9KS_GPR 0x1f /* General purpose register */ 113 #define DM9KS_CHIPR 0x2c 114 #define DM9KS_TCR2 0x2d 115 #define DM9KS_SMCR 0x2f /* Special Mode Control Reg.*/ 116 #define DM9KS_ETXCSR 0x30 /* Early Transmit control/status Reg.*/ 117 #define DM9KS_TCCR 0x31 /* Checksum cntrol Reg. */ 118 #define DM9KS_RCSR 0x32 /* Receive Checksum status Reg.*/ 119 #define DM9KS_BUSCR 0x38 120 #define DM9KS_MRCMDX 0xf0 121 #define DM9KS_MRCMD 0xf2 122 #define DM9KS_MDRAL 0xf4 123 #define DM9KS_MDRAH 0xf5 124 #define DM9KS_MWCMD 0xf8 125 #define DM9KS_MDWAL 0xfa 126 #define DM9KS_MDWAH 0xfb 127 #define DM9KS_TXPLL 0xfc 128 #define DM9KS_TXPLH 0xfd 129 #define DM9KS_ISR 0xfe 130 #define DM9KS_IMR 0xff 131 /*---------------------------------------------*/ 132 #define DM9KS_REG05 0x30 /* SKIP_CRC/SKIP_LONG */ 133 #define DM9KS_REGFF 0xA3 /* IMR */ 134 #define DM9KS_DISINTR 0x80 135 136 #define DM9KS_PHY 0x40 /* PHY address 0x01 */ 137 #define DM9KS_PKT_RDY 0x01 /* Packet ready to receive */ 138 139 /* Added for PXA of MAINSTONE */ 140 #ifdef CONFIG_ARCH_MAINSTONE 141 #include 142 #define DM9KS_MIN_IO (MST_ETH_PHYS + 0x300) 143 #define DM9KS_MAX_IO (MST_ETH_PHYS + 0x370) 144 #define DM9K_IRQ MAINSTONE_IRQ(3) 145 #else 146 #define DM9KS_MIN_IO 0x300 147 #define DM9KS_MAX_IO 0x370 148 #define DM9KS_IRQ 3 149 #endif 150 151 #define DM9KS_VID_L 0x28 152 #define DM9KS_VID_H 0x29 153 #define DM9KS_PID_L 0x2A 154 #define DM9KS_PID_H 0x2B 155 156 #define DM9KS_RX_INTR 0x01 157 #define DM9KS_TX_INTR 0x02 158 #define DM9KS_LINK_INTR 0x20 159 160 #define DM9KS_DWORD_MODE 1 161 #define DM9KS_BYTE_MODE 2 162 #define DM9KS_WORD_MODE 0
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