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The design of a renewable energy inverter involves many tradeoffs, including cost, electrical specifications, efficiency, features, reliability, installation cost, etc. Adding to these assorted considerations is the radically improved performance of SiC versus silicon-based semiconductors and their cost differences, which makes evaluating various topology options like comparing apples to oranges and pears. Models for efficiency, cost, and reliability are needed to optimize tradeoffs and to dependably predict their overall effects. This note focuses on semiconductor power loss estimations to model efficiency of solar inverters utilizing UnitedSiC cascodes and diodes in three-level versus two-level topologies with an input booster. What we are trying to answer here is when to use which topology.