热门技术

UnitedSiC’s FET product line is built on the core technology of a High-Voltage, Normally-On SiC JFET coupled with a Low Voltage, Normally-Off Silicon MOSFET in a cascode configuration. Given the cascode configuration of the SiC JFET and Si MOSFET, the MOSFET is connected to the Gate and Source pins of a package, and it the limiting device when it comes to ESD capability. The JFETs are p-n junctions and can handle far more ESD than the MOSFET. Our MOSFETs use integrated diodes as ESD protection, and the size and capacitance of the MOSFET become the determining factor in ESD capability.